Scalable and deterministic timing-driven parallel placement for FPGAs
This thesis describes a parallel implementation of the timing-driven VPR 5.0 simulated-annealing placement engine. By partitioning the grid into regions and allowing distant data to grow stale, it is possible to consider a large number of non-conflicting moves in parallel and achieve a deterministic...
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| Language: | English |
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University of British Columbia
2011
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| Online Access: | http://hdl.handle.net/2429/38168 |