Design-rule independent layout generation of PLA and gate matrix layouts for CMOS technologies
Automatic layout generation techniques can be used to generate layouts in arbitrary technologies if sufficient information describing the technology is available, and if sufficient constraints can be applied to device placement and routing. Two approaches can be taken to the automatic generation of...
| Main Author: | |
|---|---|
| Language: | English |
| Published: |
University of British Columbia
2010
|
| Online Access: | http://hdl.handle.net/2429/27880 |