An analytical model of logic resource utilization for FPGA architecture development
Designers constantly strive to improve Field-Programmable Gate Array (FPGA) performance through innovative architecture design. To evaluate performance, an understanding of the effects of modifying logic blocks structures and routing fabrics on performance is needed. Current architectures are evaluat...
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| Language: | English |
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University of British Columbia
2010
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| Online Access: | http://hdl.handle.net/2429/19753 |