| Summary: | According to International Technology Roadmap for Semiconductor 2003 (ITRS'03), by 2013
over 90% o f the total System-on-a-Chip (SoC) area will be occupied by memories, e.g., SRAMs.
The increasingly dense embedded SRAMs (e-SRAMs) are more prone to manufacturing defects
and field reliability problems since they are subject to aggressive design rules. On the one hand,
this reduces the memory and SoC yield, thereby increasingly making redundancy necessary; on
the other hand, it poses significant test challenges, particularly, the test time required for
achieving acceptable test quality. This thesis focuses on reducing test time of e-SRAMs, for both
a single and multiple memories.
In practice, the test time for a single e-SRAM consists of the time for testing Data Retention
Faults (DRFs) and the time for testing other faults named as non-DRFs. B y tightly coupling the
coupling fault (one of non-DRFs) test and hard repair techniques, here the non-DRF test time is
reduced by up to a factor of two compared with the one when not coupling those test and repair
activities. And this reduction is achieved without negatively impacting defect coverage. Based on
the memory sizes, its DRF test time is reduced by either using a Design-for-Test (DFT)
technique referred to as Pre-Discharge Write Test Mode (PDWTM) or by reusing the inherent
read or write operation time due to the access to different cells. Furthermore, by considering (i)
the trade-off values between the yield gain and the redundancy area overhead, (ii) the delay time
for DRF tests, as the two deciding factors, any e-SRAM can be categorized into one of four
groups. Based on their repair features and DRF test method selections, those four groups are
named as NSRDF e-SRAMs (with No or Soft Repair and DFT techniques for retention faults),
SRDE (with Soft Repair and the reduced DElay time for retention faults), HRDE (with Hard
Repair and the reduced DElay time for retention faults) an HRDF (with Hard Repair and DFT techniques for retention faults). Accordingly, four customized March test algorithms, generated
from a comparison algorithm, are selected for each group respectively. With the proposed
customized algorithms, the test time of any single e-SRAM can be reduced by a factor of up to
two compared with that required when applying a universal March algorithm.
Moreover, the thesis also targets on reducing the test time of multiple distributed small e-
SRAMs. To the best of our knowledge, the widely used solutions to test/diagnose such multiple
e-SRAMs are to apply serial memory interfacing techniques, i.e., unidirectional and bidirectional
serial interfaces. The approach in this thesis speeds up the referred test solutions by replacing
global serial response analyzers with parallel local response analyzers. The serial fault masking
and defect-rate dependent diagnosis existing in uni-directional/bi-directional serial interfaces are
overcome by designing a pair of serial to parallel and parallel to serial converters. When more e-
SRAMs are tested in parallel, the accumulate test power might be over the limit and thus a
power-constrained scheduling is called for. To further reduce the test time during this
scheduling, in this thesis, a "retention-aware" test power model is proposed to replace the
original "single-rectangle" model typically used for SoC cores. === Applied Science, Faculty of === Electrical and Computer Engineering, Department of === Graduate
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