SoC interconnect architecture design and evaluation under timing constraints
System on chip design steadily evolves toward different non-overlapping abstraction levels. Very different competence and design tools will be needed at each level. One specific level of abstraction will deal with interconnect technologies, with a pronounced trend towards networks on chip. It is...
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| Format: | Others |
| Language: | English |
| Published: |
2009
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| Online Access: | http://hdl.handle.net/2429/15310 |