A SAR-based Delay-Locked Loop with Duty-Cycle Correction
碩士 === 國立雲林科技大學 === 電機工程系 === 107 === All-digital delay-locked loops (ADDLLs) have been widely applied in clock synchronization due to the advantage of smaller area, lower power and shorter locking time. The successive approximation register-controlled delay-locked loop (SARDLL) adopts the binary se...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/g2gb3w |