Flow Field Visualization of a FOUP Under Different EFEM Arrangements During Open Door Condition
碩士 === 國立臺北科技大學 === 能源與冷凍空調工程系 === 107 === As the gate length of integrated circuits shrinks, the yield of semiconductor processes is challenged, and contamination-free manufacturing has become the most critical factor in semiconductor high-tech processes, especially integrated circuit manufacturing...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/f77m99 |