Design and Implementation of Ethernet Packet Transformation and Transmission Interface ASIC using UDP and Hi-Speed USB Interface

• Main Authors: LI, ZI-YU, 李子宇
• Other Authors: SUNG, GUO-MING
• Format: Others
• Language: zh-TW
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/cgnve5

碩士 === 國立臺北科技大學 === 電機工程系 === 107 === This thesis proposes a system of chip to complete the packet transformation and transmission between ethernet and USB 2.0 interface. The ethernet packet adopts the IEEE 802.3 standard frame format, where the packet is built on the GMII protocol for Gigabit Ethernet network with the advantages of high expandability and high transfer speed. The circuit architecture is composed of ethernet and USB2.0 transceiver. The ethernet receiver parses the received packet into an ARP or UDP packet, and stores their source MAC, IP header, UDP header, source and destination ports in the registers. After checking the correctness of the packet, the following procedure will be proceeded. If it is an ARP packet, it will return the ARP reply packet to provide the MAC address of the chip to the device which requested. If it is a UDP packet, after confirming that the packet information is correct, the data will be stored in the SRAM, and wait for the USB module to take out and to transfer the data at any time. After the USB receiver receives the data, the Ethernet transmitter will read the source address, IP header, UDP source and destination port in the register, and add them to the data received by the USB 2.0 receiver to complete the data transformation and transfer. Finally, an FPGA (Intel DE10-Standard) development board is used to verify the designed function and an ASIC is implemented in TSMC 0.18-μm CMOS process by passing through processes such as Synthesis, APR, DRC/LVS. Different from the traditional solutions based on software as a data acquisition system, this research is implemented by hardware, which can greatly improve the processing efficiency of data throughput to 961.69Mbps. The measured results show that the area is approximately 1.19884 x 1.1956 mm2, the dynamic power is about 74.68 mW at the power supply of 1.8 V and the operating frequency of 125 MHz / 48 MHz, and the gate count is 50,100 gates.