2.4-GHz Integer-N Phase-Lock Loop
碩士 === 國立臺北科技大學 === 電子工程系 === 107 === This paper presents a fully-integrated 2.4 GHz phase-locked loop (PLL) on standard 0.18-μm CMOS process. Utilizing the delay cell Ring Oscillator and high speed true single phase clock (TSPC) divider, the 2.4 GHz PLL achieves low power consumption of 9.45 mW. In...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2019
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/374833 |