An Innovative Structure Using Linear Drift Doping for High Voltage Power SOI LDMOS Device
碩士 === 亞洲大學 === 資訊工程學系 === 107 === The Power SOI stands for: Silicon on Insulator. In this thesis, an Ultra-high voltage triple RESURF lateral double-diffused MOS (LDMOS) in the BCD Integration process is developed and successfully simulated. The proposed triple RESURF LDMOS is able to achieve a Low...
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| Format: | Others |
| Language: | en_US |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/cdhfk3 |
| Summary: | 碩士 === 亞洲大學 === 資訊工程學系 === 107 === The Power SOI stands for: Silicon on Insulator. In this thesis, an Ultra-high voltage triple RESURF lateral double-diffused MOS (LDMOS) in the BCD Integration process is developed and successfully simulated. The proposed triple RESURF LDMOS is able to achieve a Low specific on-state resistance of 137 mohm.mm2 while maintaining a breakdown voltage of 136 volts on power SOI device. The key feature of this novel device is linear shaped P-top rings which are located on the surface of the n-drift region. Optimization of linear P-top mask design is performed in order to achieve low on-state resistance while maintaining the desired breakdown voltage with low electric field. The conventionally uniform doping has power dissipation. The problem is peak temperature is near drain side so the objective is to shift to high temperature to source side to get uniform temperature or lower the peak temperature.
The linear doping device is able to shift the high temperature near the source side. We have proactively tried to find to have a linearly doping drift for an improved Ron. Linear drift doping is used for RESURF temperature. Linear p-top. We are able to shift the peak temperature to source side and reduce the peak temperature. Using linear p-top Id_linear is higher so switching speed is faster.
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