Design of Low Temperature Sensitivity CMOS Relaxation Oscillator
碩士 === 國立臺灣科技大學 === 電子工程系 === 107 === This thesis describes a self-compensated-temperature relaxation oscillator that has been fabricated in standard 0.18μm CMOS technology. The overall chip area is 563x628μm2 (including IO PADs) and the power consumption of 22.87μW at the typical corner. The propos...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/s4u78q |