Design and Implementation of 14 bit Pipeline-SAR ADCs with a Background Nonlinearity Calibration Scheme
碩士 === 國立臺灣科技大學 === 電子工程系 === 107 === The Thesis focused on designing a high-speed and high-resolution Analog-to-Digital Converter (ADC) in advanced nanometer CMOS fabrication. In order to apply communication and graphics system, the author uses a pipelined-SAR ADC combined with background calibrati...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/2n665a |