The Design and Implementation of an All-Digital Phase-Locked Loop on FPGA
碩士 === 國立臺灣科技大學 === 電子工程系 === 107 === A lot of fast-lock-in all-digital phase-locked loops (ADPLL) have been proposed, but they usually come with large area cost and power consumption. For those low-end sensor devices, low-power and low-cost ADPLLs are required. A fast-lock-in feature is also desire...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/72pc2q |
| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 107 === A lot of fast-lock-in all-digital phase-locked loops (ADPLL) have been proposed, but they usually come with large area cost and power consumption. For those low-end sensor devices, low-power and low-cost ADPLLs are required. A fast-lock-in feature is also desired so that microcontroller can wake up quickly from sleep mode to run mode.
In this thesis, a complete all-digital phase-locked loop for clock generation is proposed. A multiplexer-chain-based digitally controlled oscillator (DCO) is designed into two modes: the oscillating mode and the time-to-digital conversion (TDC) mode.
Hence the DCO can be used to capture the input frequency at the beginning to improve lock-in time and then work as oscillator later. As a consequence, the ADPLL can achieve faster lock-in time at a small cost by reusing the delay line. This thesis also proposes a fine-tuning delay cell made of FPGA primitives in which it can achieve 0.137-ns resolution on FPGA.
The proposed ADPLL is implemented on Xilinx Virtex-5 V5LX110T. It uses 471 LUTs and 179 registers. The ADPLL output range is from 8.22 MHz to 78 MHz and can enter lock-in status within ten cycles. The peak-to-peak jitter is 0.154 ns with the output frequency of 75 MHz.
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