The Design and Implementation of an All-Digital Phase-Locked Loop on FPGA
碩士 === 國立臺灣科技大學 === 電子工程系 === 107 === A lot of fast-lock-in all-digital phase-locked loops (ADPLL) have been proposed, but they usually come with large area cost and power consumption. For those low-end sensor devices, low-power and low-cost ADPLLs are required. A fast-lock-in feature is also desire...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2019
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/72pc2q |