| Summary: | 碩士 === 國立臺灣科技大學 === 資訊工程系 === 107 === As the rapidly growing demand for system-level integration, package substrates has become one of the most important carriers in semiconductor industry.
Fine pitch ball grid array (FBGA) packaging is a widely used technology thanks to its relative cost-effectiveness compared to other advanced packaging technologies. In the FBGA substrate routing, there is a mismatched via dimension problem owing to the mechanical processes. Such mismatched issue increases the design complexity in a tightly resource-constrained substrate design. Due to various design requirements and the mismatched via dimension in FBGA substrate designs, most substrate interconnects are still customized by experienced layout engineers. However, manual substrate routing is a time consuming and error-prone task. In this thesis, we present a three-stage framework for an integer linear programming (ILP) based substrate router. The proposed framework includes the via prediction stage, the global optimization stage, and the rip-up and reroute stage. Experimental results reveal that the proposed framework achieves almost the same routing quality with average 295X speedup on 6 industrial designs.
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