A 0.02mm2 Sub-Sampling PLL with Spur Reduction Technique in 90nm CMOS Technology

碩士 === 國立臺灣大學 === 電子工程學研究所 === 107 === The thesis implements a small area sub-sampling phase-locked loop(PLL) with spur reduction technique. Nowadays, CPUs adopt a number of PLLs for individual core in order to save the power consumption by dynamically adjusting the operation frequency. Along with t...

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Bibliographic Details
Main Authors: You-Rong Qiu, 邱宥榮
Other Authors: Chung-Ping Chen
Format: Others
Language:en_US
Published: 2019
Online Access:http://ndltd.ncl.edu.tw/handle/qaj24j