| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 107 === Nowadays, Si CMOS manufacturing technology has come to 7 nm technology node and approached its physical limit. New materials that offer high carrier mobility and lead to low power consumption are the focus of research in semiconductor field. For example, III-V compound semiconductor, Among the potential options, InGaAs and Ge, which has high electron and hole mobility, respectively, are one of the best chooses for n-channel and p-channel materials. For the purpose of mass production, heterogenerous integration of InGaAs and Ge on Si substrate monolithicallly is essential. This work demonstrates n-channel fin field-effect transistors (FinFETs) based on InGaAs selectively grown in Ge trench on Si wafers.
In this study, FinFETs based on bulk InGaAs/InAlAs epiwafers are fabricated for process development and optimization in the begining. These InGaAs FinFETs exhibit a maximum drain current density of 250 µA/µm, an Ion/Ioff ratio of 104, a subthreshold swing (S.S.) of 331 mV/dec and a gate leakage current below 1×10-4 µA/µm. Devices are then fabricated based on the InGaAs nanostructure selectively grown on patterned Ge templates, which are grown on silicon-on-insulator (SOI) wafers. InGaAs and Ge FinFETs have a channel width and gate length of 100 nm/400 nm and 80 nm/400 nm, respectively. The n-InGaAs FinFETs and Ge FinFETs exhibit an Ion/Ioff ratio of 10 and 104, a maximum drain current density of 118 µA/µm and 7.5 µA/µm, and a subthreshold swing (S.S.) of 650 mV/dec and 90 mV/dec, respectively. The gate leakage current density of both InGaAs and Ge FinFET is below 1×10-4 µA/µm.
This work successfully demonstrates the heterogenerous integration of GaAs and Ge FinFETs on Si substrates. Better device performance can be obtained by improving the selective growth and high-k gate-stack processes.
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