Line-Rate Network Applications in P4 Switches
碩士 === 國立交通大學 === 網路工程研究所 === 107 === This thesis designs and develops two P4 (Programming Protocol-Independent Packet Processor) applications in commercial P4 switches. The first P4 application is packet aggregation and disaggregation. We propose a novel approach that utilizes the header manipulati...
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| Format: | Others |
| Language: | en_US |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/62rgew |
| Summary: | 碩士 === 國立交通大學 === 網路工程研究所 === 107 === This thesis designs and develops two P4 (Programming Protocol-Independent Packet Processor) applications in commercial P4 switches. The first P4 application is packet aggregation and disaggregation. We propose a novel approach that utilizes the header manipulation of the P4 switch to aggregate small packets into large packets and disaggregate large packets back into small packets. Our study indicates that packet aggregation can be achieved in a P4 switch with its line rate. On the other hand, to disaggregate a packet that combines N IoT messages, the processing time is about the same as processing N individual IoT messages. We further propose to provide a small buffer in the P4 switch to significantly reduce the processing power for disaggregating a packet. Another P4 application is heavy hitter detection, which is considered as an important mechanism to identify outliers in network traffic. This thesis develops HashPipe as a soft computing application in a real P4 switch and shows that this implementation is not trivial. We describe how to smartly utilize the atoms of the Banzai machine to implement HashPipe in the P4 switch. Then we propose an enhanced HashPipe algorithm that improves the accuracy of the original HashPipe by up to 80%.
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