Evaluation of Gate Reliability on Charge-trapping Gate Stack In E-mode GaN MIS-HEMT

• Main Authors: Meng, Shu-Yun, 孟書筠
• Other Authors: Chang, Yi
• Format: Others
• Language: en_US
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/qx8dgx

碩士 === 國立交通大學 === 工學院半導體材料與製程設備學程 === 107 === E-mode GaN MIS-HEMT was evaluated by PBTI and TDDB. First, gate recessed E-mode GaN MIS-HEMT is a common device structure for gate is reduced by etching process, reduces the resulting in the low concentration of Two-Dimensional Electron Gas (2DEG) underneath the gate, therefore, the device achieve on E-mode operation. In addition, inserting a gate and under the gate can further increase the operating voltage of the device, greatly reduce the gate leakage current. However, this device with gate dielectric is accompanied many possible trapping states in the gate dielectric layer, these trapping states could be a concern for the device reliability and stability. Thus it is the motivation in this work. In order to examine the device stability and lifetime, the PBTI and TDDB were utilized for the gate reliability evaluation.