Process Optimization of Through Silicon Vias Metallization Using Reduced Graphene Oxide as a Conductive Layer
碩士 === 國立中興大學 === 化學工程學系所 === 107 === Three-dimensional (3D) IC chip stacking has been proposed for a long time. An interposer designed between two chips for interconnection [i.e., through silicon vias (TSVs)] is a bridge for vertical signal transmission. Recently, reduced Graphene Oxide (rGO) has a...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/eap62d |