Altera Based HLS Implementation on Loop Intensive Algorithm Performance and Analysis
碩士 === 輔仁大學 === 資訊工程學系碩士班 === 107 === This thesis explores the usage of High Level Synthesis (HLS) on loop intensive algorithms on Altera and its performance analysis. Besides, usage of this tool on FPGA for these algorithms can improve the performance speed. Most of the HLS research is based on Xil...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/3juqu4 |