| Summary: | 碩士 === 國立雲林科技大學 === 電子工程系 === 106 === In this work, 4-mask amorphous InGaZnO channel passivated TFT (a-IGZO CHP TFT) is simulated by technology computer aided design (TCAD), to investigate effects of source/drain (S/D) parasitic field-plates (FPs). Electrical characteristic and active layer carrier conduction are investigated to explore the corresponding physical mechanisms.
Influences of a-IGZO back surface damage induced by plasma-enhanced chemical vapor deposition (PECVD) passivation deposition and source/drain contact hole etching process would lead to defect created to cause the performance degradation and limit carriers transport. For this reason, to find a method to recover the TFT performance without using additional lithography processes is urgent. In this study, the device model is established based on a fabricated 4-mask a-IGZO CHP TFT by TCAD. Besides, we purposed a novel design which using the extended drain electrode as a parasitic FP or a virtual top-gate (TG) to improve the TFT performance.
Moreover, effects of parasitic S/D FPs on the TFT performance under different thicknesses of CHP (tCHP) and a -IGZO layer (tIGZO) will also be examined. Simulation results show that drain FP with an ideal can induce carriers in the a-IGZO layer to activate back channel conduction to enhance the TFT performance. However, to further understand the effects of the parasitic S/D FPs on the TFT I-V and performance. The corresponding physical mechanism verifies the validity of this simulated curves, current flow patterns and carrier concentration distribution will be explored.
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