| Summary: | 碩士 === 國立雲林科技大學 === 電子工程系 === 106 === The clock skew is a common problem in the design of digital systems. It is due to the clock signal of the digital system. The length of the circuit between the system function blocks and the capacitive load are different, and the time difference of the clock received by different circuit blocks is different. The problem is that the higher the operating frequency of digital systems, the more dangerous the problem of clock skew. In the large-scale digital systems generally use Phase Locked Loop (PLL), or Delay Locked Loop (DLL) to deal with the clock skew problem. Although both PLL and DLL can achieve clock synchronization and solve the problem of clock signal skew, if the circuit block does not need to do frequency synthesis in applications, the use of DLL in the circuit design will be relatively simple, so this thesis focuses on DLL Chip circuit design. Besides, due to the very high operating frequency of today's systems, the phase error after the DLL is locked severe. Also, the current digital system has a wide range of operation of the clock for energy-saving design. It is a challenge for the DLL to take into account the system clock frequency range and phase locked error. For DLL circuits, the key to reducing the DLL phase error is the resolution of the delay line, but the high-resolution delay line is not conducive to full frequency design. Therefore, the variable delay time provided by the delay line in the DLL also needs to be changed flexibly, to balance the high burden of high-phase resolution and the low-level delay in the number of delay lines. Although traditional DLLs also provide superior phase-locking accuracy and stability. However, few DLLs have both high resolution and high-frequency bandwidth, and the problem is that the lock-up time is long and the delay time between charge and discharge of the delay line causes a change in the duty cycle. The traditional literature also intuitively adopts the design of the course and fine weighted delay lines in determining the extensive frequency operation. However, after research and analysis, traditional coarse and fine delay lines will have different delay paths due to different paths when switching between different paths, which in turn makes the overall phase locking error of the DLL unable to decrease.
This thesis proposes a gate-controlled non-path-selection fine variable delay line circuit. This circuit can generate very slight delay time changes under different logic states. Since the controllable delay time of the circuit in each delay unit, the delay line formed by it does not need the conventional path selection and reduces the error when changing the delay time. This circuit can generate coarse and fine delay times in the same delay cell circuit through proper size adjustment design. The re-designed delay locked loop with coarse and fine adjustment and binary search mechanism can work in the frequency range of 850MHz - 4.5GHz to solve the problem of the frequency range and high resolution. The core circuit implemented by TSMC CMOS 40nm process, the input voltage is 0.9V, and the area is 0.0034mm2. According to the post-layout simulation results, the power consumption is 1.708mW, and the phase error is less than 0.5ps.
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