An All Digital Sub-picosecond Gate Controled Loading Delay Locked Loops
碩士 === 國立雲林科技大學 === 電子工程系 === 106 === The clock skew is a common problem in the design of digital systems. It is due to the clock signal of the digital system. The length of the circuit between the system function blocks and the capacitive load are different, and the time difference of the clock rec...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/z839e8 |