| Summary: | 碩士 === 國立臺灣科技大學 === 電機工程系 === 106 === Dynamic Random Access Memory (DRAM) is widely used in most modern electronic systems as main memory because of its high density, longevity, and low cost. As the VLSI technologies keep shrinkage and minimization of devices, the yield and reliability of DRAM has been severely affected due to the occurrences of soft errors and permanent faults. Moreover, the data retention time of DRAM cells is limited by inherent leakage current, temperature spans, and aging effects. In order to prevent from data retention faults, periodic refresh operations which devour energy and degrade system performance are required. Fortunately, there are many techniques proposed for protecting DRAM by using the error correction code (ECC) or replacing faulty cells with redundancies. However, most of previous techniques address different fault models separately. In order to conquer these fault models simultaneously with limited repair resources, integrated highly reliable and low-power design techniques are proposed in this thesis.
The adaptive block-based refresh technique and the hybrid ECC and redundancy techniques are integrated in the integrated techniques. When the memory system is used on-line and executes a read operation, the faulty codeword will be complemented and written back again for discriminating hard errors. Thereafter, spare bits can be used to replace the memory cells with hard errors. In order to distinguish the data retention errors, an extra read operation will be issued after the time duration of the original refresh period for this memory word when it is detected faulty. Then the refresh period of refresh region containing this word will be halved to prevent loss of data. Thereafter, the correction capability of the adopted ECC can be used to protect soft errors.
The corresponding hardware architecture of our technique is also proposed in this thesis. We also develop a simulator to evaluate the repair rate, yield, and the reliability. Hardware overhead and refresh power are analyzed, too. According to experimental results, the proposed technique can improve yield, repair rate, and reliability significantly. Furthermore, the refresh power can be saved up to 87.16% with less than 1% hardware overhead for a 128Mb DRAM.
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