The Efficient VLSI Design and Implementation of Neural Networks Based on Depthwise Separable Convolution
碩士 === 國立臺灣科技大學 === 電子工程系 === 106 === This thesis presents the efficient VLSI architecture design and circuit implementation for a Neural Network based on the depthwise separable convolution. The design proposed in this thesis, to the best of the knowledge, depicts the first hardware accelerator for...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/ta436p |