Clock-less DFT for Dual-rail Asynchronous Circuits
碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === Because there is no clock signal and there are many non-scan state-holding elements, it is a real challenge to test asynchronous circuits. In this thesis, we propose asynchronous circuit scan (A-scan) latch, which can flip between Valid and Empty so that we ca...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/d59jm5 |