All Digital Capacitance Calibration for Successive-Approximation Register Analog-to-Digital Converter
碩士 === 國立臺灣大學 === 電子工程學研究所 === 106 === This thesis presents a 12-bit 1 MS/s high power-efficient successive approximation register (SAR) analog-to-digital converter (ADC) with 0.7V supply voltage. By using detect-and-skip (DAS) algorithm, the capacitive digital-to-analog converter (DAC) switching po...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/btzwa7 |