Twin Mode Non-Volatile Logic Gates By FinFET CMOS Logic Process

碩士 === 國立清華大學 === 電子工程研究所 === 106 === abstract hide

Bibliographic Details
Main Authors:	Chien, Wei-Yu., 錢威宇
Other Authors:	King, Ya-Chin
Format:	Others
Language:	zh-TW
Published:	2018
Online Access:	http://ndltd.ncl.edu.tw/handle/hg5d92

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record_format	oai_dc
spelling	ndltd-TW-106NTHU54280282019-05-16T00:15:33Z http://ndltd.ncl.edu.tw/handle/hg5d92 Twin Mode Non-Volatile Logic Gates By FinFET CMOS Logic Process 應用於鰭式場效電晶體邏輯製程之可調式非揮發性邏輯閘研究 Chien, Wei-Yu. 錢威宇碩士國立清華大學電子工程研究所 106 abstract hide King, Ya-Chin 金雅琴 2018 學位論文 ; thesis 59 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立清華大學 === 電子工程研究所 === 106 === abstract hide
author2	King, Ya-Chin
author_facet	King, Ya-Chin Chien, Wei-Yu. 錢威宇
author	Chien, Wei-Yu. 錢威宇
spellingShingle	Chien, Wei-Yu. 錢威宇 Twin Mode Non-Volatile Logic Gates By FinFET CMOS Logic Process
author_sort	Chien, Wei-Yu.
title	Twin Mode Non-Volatile Logic Gates By FinFET CMOS Logic Process
title_short	Twin Mode Non-Volatile Logic Gates By FinFET CMOS Logic Process
title_full	Twin Mode Non-Volatile Logic Gates By FinFET CMOS Logic Process
title_fullStr	Twin Mode Non-Volatile Logic Gates By FinFET CMOS Logic Process
title_full_unstemmed	Twin Mode Non-Volatile Logic Gates By FinFET CMOS Logic Process
title_sort	twin mode non-volatile logic gates by finfet cmos logic process
publishDate	2018
url	http://ndltd.ncl.edu.tw/handle/hg5d92
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Twin Mode Non-Volatile Logic Gates By FinFET CMOS Logic Process

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