Twin Mode Non-Volatile Logic Gates By FinFET CMOS Logic Process
碩士 === 國立清華大學 === 電子工程研究所 === 106 === abstract hide
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/hg5d92 |