Implementations on X/Ka-band CMOS Wideband Unilateralized Power Amplifiers and X-band GaN Power Amplifiers with Low Impedance Binary Power Combining Technique and Doherty Architecture

• Main Authors: Yun-Jhu Lai, 賴畇茿
• Other Authors: 邱煥凱
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/e24f34

碩士 === 國立中央大學 === 電機工程學系 === 106 === The thesis developed five power amplifiers that were designed in tsmcTM 0.18-µm CMOS, tsmcTM 90-nm CMOS and WINTM 0.25-µm GaN for both X-band and Ka-band operations. The best transistor size and biasing current density of the used transistors were chosen by simulating in different processes. The wideband matching was realized by the magnetically coupling transformer and the enhanced efficiency was realized by using Doherty architecture. Finally, the circuit performance was verified by the measuring small and large signal parameters, such as S-parameters, output power, linearity and modulated signals, etc., The first power amplifier was fabricated in tsmcTM 0.18-µm CMOS technology for X-band operation. This two-stage power amplifier adopted the unilateralization technique which was constructed by a class A amplifier in parallel with class B one to increase the overall output 1-dB compression power (OP1dB) and power added efficiency (PAE). The wide operating bandwidth was achieved by using magnetically coupling Balun for the output matching and T-type matching for the inter-stage matching. The measurement results showed a small signal gain of 20.1 dB, the saturated output power (Psat) and OP1dB are 20.1 dBm and 18.4 dBm, respectively. The peak output power and PAE are improved by the amount of 3.8 dB and 3.4%, respectively, while adopted this composited power amplifier architecture. The chip area is 1.78 (1.95×1.13) mm2. The second and third chips were fabricated in tsmcTM 90-nm CMOS technology for Ka-band operation. Two amplifiers were realized by using unilateralization technique in common-source topology. The input and output matching design followed the previous work and the inter-stage matching was realizes by magnetic transformer. The third power amplifier applied a pre-matching design to minimize the chip size and increase the operating bandwidth. These power amplifiers displayed the gains of 17.43 dB and 14.5dB, respectively. The saturated output powers were measured to 14.73 dBm and 18.4 dBm. The OP1dB were 10.7dBm and 14.5 dBm, respectively. The chip areas are 0.73 (1.41×0.405) mm2 and 0.67 (1.01×0.67) mm2. The fourth chip presents an X-band monolithic microwave integrated circuit (MMIC) binary-combining power amplifier in WINTM 0.25-µm GaN technology. The output of the two-stage CS power amplifiers combined two circuit paths to double the output power and the low impedance combiner reduced the power loss. The measured results exhibited a peak gain of 16.35 dB, a saturation output power of 33.2dBm and an OP1dB of 24.5dBm. The chip area is 3.47 (1.98×1.75) mm2. The fourth chip presents an X-band monolithic microwave integrated circuit (MMIC) binary-combining power amplifier in WINTM 0.25-µm GaN technology. The output of the two-stage CS power amplifiers combined two circuit paths to double the output power and the low impedance combiner reduced the power loss. The measured results exhibited a peak gain of 16.35 dB, a saturation output power of 33.2dBm and an OP1dB of 24.5dBm. The chip area is 3.47 (1.98×1.75) mm2. The last power amplifier also was fabricated in WINTM 0.25-µm GaN technology. A Doherty power amplifier (DPA) adopted a T-type network for the output matching to reduce the chip size and a Lange-coupler for the input matching. The DPA achieved a peak gain of 11.8 dB, a saturation output power of 35.9 dBm, a PAE at 6-dB power back-off of 39.9% and a peak PAE 41.5%. The chip area is 3.03 (1.73×1.75) mm2.