On Clocking and Placement Techniques for Nanometer Designs
博士 === 國立交通大學 === 電子研究所 === 106 === Placement and clock are two fundamental engines in physical implementation. With supply voltage decreasing for low power, voltage variation induced timing uncertainty is no longer negligible. To meet timing spec, designers have to adapt mesh and spine as clock net...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/j222au |