| Summary: | 博士 === 國立交通大學 === 資訊科學與工程研究所 === 106 === Standard cells are basic and extensively used components in digital IC designs. They are optimized manually to realize high design quality. Several standard cell libraries have been developed based on different objectives such as delay or power consumption for satisfying the associated VLSI design objectives. However, as feature sizes continue to shrink, complex design rules that arise owing to design for manufacturing (DFM) considerations complicate the design of standard cell layouts and therefore substantially increase the layout designer’s burden and hinders the design process. Automated cell layout synthesis can overcome these problems.
In recent years, restricted design rule (RDR) has been proposed to reduce the set of design rules while maintaining design quality by using the key concept of regularity. With the RDR concept, we can easily address DFM concerns in cell layout designs without sacrificing design quality. However, regularity restricts the design freedom and thus layout designers have less room for improving the layout quality; this has hastened the development of automated cell layout synthesis because regularity enables automated synthesized layouts to have similar or even better design qualities compared with manual designs and requires less design time.
In this thesis, we present a robust standard cell layout synthesis framework that considers complex design rules in advanced technology nodes. A dynamic programming–based transistor placement algorithm is proposed to simultaneously consider the cell area and the routability of within-cell routing. Then, a LEGO-like assembling method is adopted to efficiently and effectively overcome the challenge of different folding styles. Next, a fast and accurate routing planning is used to estimate the available and required routing resources and to then provide a rough routing result considering complex design rules. This routing planning can then guide the router to find a routing result that minimizes the required routing resource. This framework successfully synthesizes more than 1000 standard cells with competitive qualities relative to commercial cell libraries under commercial 28-nm technology nodes. Next, we develop a pin accessibility evaluation model for standard cell layouts. Cell layout designers can use this accurate estimation model to optimize the pin accessibilities of cell layouts in order to optimize the routability of VLSI designs. Our experimental results indicate that VLSI design with higher pin accessibility can provide better routing results in terms of total wirelength and via count. Finally, an exact multilayer pattern matching method is proposed to detect lithography-unfriendly patterns on standard cell–based designs. Manufacturing problems can accordingly be investigated and resolved in the early design stage.
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