A Robust Standard Cell Layout Synthesis and Verification Framework for Advanced Technology Nodes
博士 === 國立交通大學 === 資訊科學與工程研究所 === 106 === Standard cells are basic and extensively used components in digital IC designs. They are optimized manually to realize high design quality. Several standard cell libraries have been developed based on different objectives such as delay or power consumption fo...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/7df3x6 |