A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Time-based Adaptive Window
碩士 === 國立成功大學 === 電機工程學系 === 106 === This thesis presents a 0.35 V 100 kS/s 10-bit successive approximation register (SAR) ADC with adaptive window (AW) in 90 nm CMOS. The SAR ADC uses the transient information of the latch comparator to create redundancy ranges. Furthermore, the proposed technique...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/n8e3we |