The Low-power VLSI Design for Sorting Unit and Median Filter
博士 === 國立成功大學 === 資訊工程學系 === 106 === This thesis presents hardware design and implementation of sorting algorithm and median filter architecture. There are mainly three portion in this thesis, including the design of low-power sorting unit, design of low-power median filter, and modular design of bi...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/au8d9z |