The Design of 0.2-1.8GHz Duty Cycle Correction Circuit.
碩士 === 逢甲大學 === 電子工程學系 === 106 === In this thesis, we propose an analog high speed circuit which is fast locking and low error. It is necessary to have precise signal transmission in the modern high speed signal transmission circuit and any signal circuit which need correction. In order to avoid the...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/95ce9s |