| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 106 === Clock skew minimization is a very important task for the timing optimization of sequential circuits. As the technology node continues to shrink, the clock skew caused by the process/voltage/temperature (PVT) variations may result in a serious timing problem. To deal with this serious timing problem, the previous work proposed a self-adjusting mechanism to dynamically control the PVT-variations induced clock skew. However, the previous work requires a lot of clock buffers for dynamic clock skew control. In this thesis, we present a new mechanism to select the channels of adjustable-delay-buffers (ADBs). Based on the proposed new mechanism, the number clock buffers in the ADBs can be saved. Experimental results show that our approach works well in practice.
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