A New Dynamic Clock Skew Control Mechanism and Its Corresponding Adjustable Delay Buffer Design
碩士 === 中原大學 === 電子工程研究所 === 106 === Clock skew minimization is a very important task for the timing optimization of sequential circuits. As the technology node continues to shrink, the clock skew caused by the process/voltage/temperature (PVT) variations may result in a serious timing problem. To de...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/s6srws |