Layout Optimization of 2+1-order Switched-Current Delta-Sigma ADC with Digital Cancellation Circuit

• Main Authors: Chi-Kuang Wang, 王啟光
• Other Authors: 宋國明
• Format: Others
• Language: zh-TW
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/8y358t

碩士 === 國立臺北科技大學 === 電機工程研究所 === 105 === This paper presents a circuit layout approach to improve the performance of the two-order and multi-stage cascade triangulation analog-to-digital converters, and to reduce the wafer area. The focus is on improving the layout of analog circuits. Especially , the method described below to improve; the analysis of the number is connecting line pin and select the packaging. And then determined the input and output pin position; the circuit class based on the location of the foot from the top of the circuit began planning power lines , block circuits and connecting the line position. At each level of the block circuits, first determine the location of the power cord and wiring, and then the components of the nearest match; the circuit of a single component into at least two to layout, to match the symmetrical effect. For example, a single MOS replaced by the width of gateway halved, the gate length of two MOS, the one-dimensional and two-dimensional shared for center point matching symmetry; the use of three-dimensional concept, the metal connection.So it is used to different layers of metal and staggered connections to reduce, for that is unnecessary wiring to reduce parasitic resistance and capacitance values. After improvement, the total area of the chip is reduced by 5.52%. After the layout is improved, the effective number of bits is about 12.44 bits, and the effective bit is raised by 1.89 bits.