Layout Optimization of 2+1-order Switched-Current Delta-Sigma ADC with Digital Cancellation Circuit
碩士 === 國立臺北科技大學 === 電機工程研究所 === 105 === This paper presents a circuit layout approach to improve the performance of the two-order and multi-stage cascade triangulation analog-to-digital converters, and to reduce the wafer area. The focus is on improving the layout of analog circuits. Especially , th...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/8y358t |