Total Capacitance Minimization Clock Synthesis with Blockage-Avoiding Hybrid-Structure Network

• Main Authors: Chun-Wei Ho, 何俊瑋
• Other Authors: Shao-Yun Fang
• Format: Others
• Language: en_US
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/uzw34k

碩士 === 國立臺灣科技大學 === 電機工程系 === 105 === Circuit delay has become a crucial concern in high performance VLSI system, and is increasingly affected by process variation at nano-node technologies. Additionally, power dissipation of clock tree should be minimized in order to meet the system power requirement. Clock distribution networks share a huge portion of power among all chip elements. The power consumption of the clock distribution network can account for up to 40\% of the entire chip power budget. The tradeoff between the circuit delay and power consumption is hard to be dealt with. In addition, as the technology node scale below 65nm, the on-chip-variation (OCV) has become a serious concern, especially for the skew of clock network. Since the higher skew has the negative influence on the maximum clock frequency, reducing the skew variation can improve timing yield. Among the different methods suggested for process, voltage and temperature (PVT) variations reduction, clock mesh provides high robustness to variations due to the redundant path. However, clock meshes suffer from several drawbacks such as high power dissipation, difficulty in analyzing and automating because of multiple paths and many mesh nodes. By contrast, conventional clock tree structure is commonly used due to low power consumption, less routing resource usage. Nevertheless, a tree-based network is highly sensitive to PVT variations. In this thesis, we propose to use the hybrid structure that combines tree-based and mesh-based structures for power and skew trade-off methodology. First, the mesh pitch is determined initially that is based on the local skew distance provided by the ISPD 2010 contest. Next, the sink loading contained in each lattice is evaluated. If the maximum sink loading within each mesh lattice is too large to be driven by the biggest size buffer, the pitch size will be re-compute in order to shrink until the sink loading is drivable. Then, we propose a mesh loading balance algorithm to minimize the difference of sink loading in each lattice. While the construction of the mesh is settle down, the local tree in each lattice will be constructed and the local tree root will simply connect to the nearest mesh stub as the tapping point. We will treat the tapping points as the top-level tree sinks for building the top-level tree, and then we adopt extended-DME algorithm to handle the obstacle routing. Experimental results suggest that hybrid-structured clock network can minimize the total capacitance under skew constrains.