Total Capacitance Minimization Clock Synthesis with Blockage-Avoiding Hybrid-Structure Network
碩士 === 國立臺灣科技大學 === 電機工程系 === 105 === Circuit delay has become a crucial concern in high performance VLSI system, and is increasingly affected by process variation at nano-node technologies. Additionally, power dissipation of clock tree should be minimized in order to meet the system power requireme...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/uzw34k |