| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 105 === With low power and variation-tolerant features, asynchronous methodologies have been widely used in advanced VLSI designs. Testing asynchronous circuits has become a very important practical issue. This research presents a new test methodology, including design for testability (DFT) and automatic test pattern generation (ATPG), for asynchronous dual-rail circuits. The proposed DAC-scan cell is a hazard-free scan design, which can be applied to various implementations of dual-rail asynchronous circuits. Two-pattern stuck-at test and three-pattern delay test techniques are presented to detect local feedback faults in the circuits without inserting extra DFT into feedback loops. With our test methodology, we can use traditional full-scan ATPG to generate high fault coverage test patterns. Moreover, designers can trade-off between fault coverage and area overhead by using different versions of DAC-scan cells.
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