Low-Skew High-Speed Low-Power Four-Channel Time-Interleaved SAR ADC

碩士 === 國立臺灣大學 === 電子工程學研究所 === 105 === As the advantage of wireless communication system, the requirement for high speed sampling rate and medium resolution gradually increase. A 10-bit 1GS/s time-interleaved SAR ADC is presented in 40nm general process of CMOS technology in this thesis. This th...

Full description

Bibliographic Details
Main Authors:	Mi-Ti Yang, 楊蜜迪
Other Authors:	Hsin-Shu Chen
Format:	Others
Language:	en_US
Published:	2016
Online Access:	http://ndltd.ncl.edu.tw/handle/bu4g43

id	ndltd-TW-105NTU05428012
record_format	oai_dc
spelling	ndltd-TW-105NTU054280122019-05-15T23:17:02Z http://ndltd.ncl.edu.tw/handle/bu4g43 Low-Skew High-Speed Low-Power Four-Channel Time-Interleaved SAR ADC 低時脈偏移高速低功率四通道時間交錯連續漸進式類比至數位轉換器 Mi-Ti Yang 楊蜜迪碩士國立臺灣大學電子工程學研究所 105 As the advantage of wireless communication system, the requirement for high speed sampling rate and medium resolution gradually increase. A 10-bit 1GS/s time-interleaved SAR ADC is presented in 40nm general process of CMOS technology in this thesis. This thesis proposes a low-skew bootstrap to solve the timing skew problem between channels without digital calibration. In order to improve the energy-efficiency of the sub-channel, the subranging SAR ADC is used for lowing the FOM. This time-interleaved SAR ADC achieves an ENOB of 7.9 at the conversion rate of 1GS/s with 250MHz input signal. The active area is only 0.0459 mm2. It consumes 3.0245mW and gets the good FoM of 19.83fJ/conversion-step. It is suitable for the energy-efficient wireless communication and Ethernet network application. Hsin-Shu Chen 陳信樹 2016 學位論文 ; thesis 84 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	碩士 === 國立臺灣大學 === 電子工程學研究所 === 105 === As the advantage of wireless communication system, the requirement for high speed sampling rate and medium resolution gradually increase. A 10-bit 1GS/s time-interleaved SAR ADC is presented in 40nm general process of CMOS technology in this thesis. This thesis proposes a low-skew bootstrap to solve the timing skew problem between channels without digital calibration. In order to improve the energy-efficiency of the sub-channel, the subranging SAR ADC is used for lowing the FOM. This time-interleaved SAR ADC achieves an ENOB of 7.9 at the conversion rate of 1GS/s with 250MHz input signal. The active area is only 0.0459 mm2. It consumes 3.0245mW and gets the good FoM of 19.83fJ/conversion-step. It is suitable for the energy-efficient wireless communication and Ethernet network application.
author2	Hsin-Shu Chen
author_facet	Hsin-Shu Chen Mi-Ti Yang 楊蜜迪
author	Mi-Ti Yang 楊蜜迪
spellingShingle	Mi-Ti Yang 楊蜜迪 Low-Skew High-Speed Low-Power Four-Channel Time-Interleaved SAR ADC
author_sort	Mi-Ti Yang
title	Low-Skew High-Speed Low-Power Four-Channel Time-Interleaved SAR ADC
title_short	Low-Skew High-Speed Low-Power Four-Channel Time-Interleaved SAR ADC
title_full	Low-Skew High-Speed Low-Power Four-Channel Time-Interleaved SAR ADC
title_fullStr	Low-Skew High-Speed Low-Power Four-Channel Time-Interleaved SAR ADC
title_full_unstemmed	Low-Skew High-Speed Low-Power Four-Channel Time-Interleaved SAR ADC
title_sort	low-skew high-speed low-power four-channel time-interleaved sar adc
publishDate	2016
url	http://ndltd.ncl.edu.tw/handle/bu4g43
work_keys_str_mv	AT mitiyang lowskewhighspeedlowpowerfourchanneltimeinterleavedsaradc AT yángmìdí lowskewhighspeedlowpowerfourchanneltimeinterleavedsaradc AT mitiyang dīshímàipiānyígāosùdīgōnglǜsìtōngdàoshíjiānjiāocuòliánxùjiànjìnshìlèibǐzhìshùwèizhuǎnhuànqì AT yángmìdí dīshímàipiānyígāosùdīgōnglǜsìtōngdàoshíjiānjiāocuòliánxùjiànjìnshìlèibǐzhìshùwèizhuǎnhuànqì
_version_	1719143798409265152

Low-Skew High-Speed Low-Power Four-Channel Time-Interleaved SAR ADC

Similar Items