| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 105 === Because analog circuits are often very sensitive, it is important to consider non-ideal effects in design stage. In order to reduce the impact of non-ideal effects on circuit performance, the layouts of analog circuits are often generated manually, which requires a lot of time. Using EDA tools is a possible way to reduce design efforts, but the complex layout constraints are still a big issue for layout automation. Besides the layout placement problem, there are some literatures on analog routing, too. However, most of the researches on analog layout automation are still using digital routing methodology that sets preferred routing direction for each metal layer. This routing methodology can solve the crossing issue between nets, but an extra via is required to connect the horizontal line and vertical line. Those vias will increase the non-ideal effects on routing nets and influence the circuit performance.
This thesis proposes an analog routing flow to minimize the wire resistance at routing stage. In the proposed method, we will try to route each net without changing metal layer and consider the wire length simultaneously to reduce the parasitic effect and keep circuit performance after layout. Frist, this flow will do a preliminary planning about the routing paths and their directions to reduce the layer changing cases due to net crossing. Next, the real routing paths are determined to calculate the wire resistance based on the number of vias and wire length. Instead of wire length, the wire resistance is used in the optimization to find the best path. As shown in the experimental results, this approach is able to reduce the parasitic effects on routing nets and keep the circuit performance after layout.
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