On Minimizing Wire Load of Analog Routing for Performance
碩士 === 國立中央大學 === 電機工程學系 === 105 === Because analog circuits are often very sensitive, it is important to consider non-ideal effects in design stage. In order to reduce the impact of non-ideal effects on circuit performance, the layouts of analog circuits are often generated manually, which requires...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/62327190446737019997 |