| Summary: | 碩士 === 國立交通大學 === 電機工程學系 === 105 === The speed of SAR ADC is limited by settling time of MSB capacitor and number of converting cycle. This thesis implemented a two-bit/step algorithm for fully differential SAR ADC, and reduce over 50% settling
time of MSB capacitor. We use redundant bits to self- tolerate the mistake of settling. Since one of SAR ADC’s advantage is low power consumption, we design a reference voltage generator without component which cost lots of
power to fit the two-bit/step architecture. To avoid the need of inputting a high-frequency clock externally, the asynchronous clock is used.
We design a 9-bit SAR ADC. and the behavior model shows that it could achieve 9.18b ENOB. The circuit simulation results achieve 52.84dB SNDR, 8.48b ENOB. In the least delay case, the results achieve 48.93dB SNDR, 7.84b ENOB. The measurement results achieve 44.72dB SNDR and 7.14b ENOB, It consumes current of 1.05mA(analog part) and 0.28mA(digital part) at 1.8V supply voltage with the longest delay time in 10MS/s. And achieve 46.65dB SNDR and 7.46b ENOB, It consumes current of 1.05mA(analog part) and 0.97mA(digital part) in 35MS/s with the shortest delay time.
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