Design of a Two-bit/Step 9-bit SAR ADC with Redundant Bits
碩士 === 國立交通大學 === 電機工程學系 === 105 === The speed of SAR ADC is limited by settling time of MSB capacitor and number of converting cycle. This thesis implemented a two-bit/step algorithm for fully differential SAR ADC, and reduce over 50% settling time of MSB capacitor. We use redundant bits to self- t...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/59234214966408240212 |