Bottom-up Growth and the Electrical Property of Si Nanowires

• Main Authors: Tzou, Sheng-Jie, 鄒勝傑
• Other Authors: Chou, Yi-Chia
• Format: Others
• Language: zh-TW
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/w592ez

碩士 === 國立交通大學 === 電子物理系所 === 105 === In our research, we use the metal-catalyst growth method to grow Si nanowires on Si substrate in ultra-high vacuum chemical vapor deposition (UHV-CVD). We investigate the influence of different growth parameters on morphology and growth rate of Si nanowires in UHV-CVD and discuss the mechanism. Besides, we also measure electrical properties of Si nanowires. We find that growth the temperature significantly influence on morphology and the growth rate, thickness of metal catalyst is related to the number of nanowires on substrate. In addition to appropriate growth temperature, we also observe that substrate cleanliness is another critical point for excellent morphology of nanowires. In the other hand, growth temperature and precursor gas pressure are closely related to growth rate. For the electrical property measurement, we use e-beam lithography method to connect nanowire with the pad and measure I-V curve of the Si NWs and GaN NWs. To remove contact resistance, we adopt interpolation method which is suitable for high resistance material. The resistivity of Si nanowire is 85 (ohm"×" m). The resistivity of Si nanowire in this thesis is similar to that grown by MBE in literature. For the purpose of forming Si/GaN heterostructure, we discuss how to form clear interface in the heterostructure by alloy-catalyst growth method. Besides, we measure the resistivity of GaN NWs. The value is lower than the resistivity of GaN grown by MBE. By using the low temperature photoluminescence analysis, we confirm the multiple defects in the GaN nanowire, which result in lower resistivity.